The present invention generally relates to low density varactors.
On-chip variable capacitors (varactors) are widely used in integrated circuits for clocking and I/O applications, e.g. inductor-varactor voltage-controlled oscillators (LC VCOs) to provide a stable desired frequency, or impedance-matching circuits to reduce signal loss at chip inputs or outputs. Tuning is achieved by varying a control voltage input to the varactor, to change the capacitance value between a low and a high value. These varactors typically have high capacitance density (capacitance per unit area) to allow implementation of large capacitance values in a small chip area. Tuning such high-density varactors between the low-capacitance and high-capacitance states results in a large capacitance step, thus causing a large frequency step in an LC VCO, for example. Some circuit applications require a small frequency step, e.g. a digital PLL with separate proportional and integral feedback paths. Here the proportional path gain should be very small (kHz steps) compared to the integral path gain (MHz steps). The integral path is typically implemented using the high-density varactors. However, the proportional path needs a device that allows a small frequency step. Prior art solutions to achieve these small frequency steps include using an array of the smallest size high-density varactor allowed by the semiconductor process technology. However, such a solution requires a large chip area and adds large wiring parasitics to the varactor which reduces the VCO tuning range.
An example of prior art to achieve a small frequency step is shown in FIG. 1. A high-density varactor 100 having the smallest size allowed by the technology is connected to the tuned circuit node (e.g. the resonant tank node of LC VCO), and a digital control (CAP_HI) is set to 1 to provide the maximum capacitance on the tank node, or 0 to provide the minimum capacitance. An array of these varactors is connected in parallel to provide the desired total capacitance. The disadvantages of this method are the large chip area required for the array and the large wiring parasitics of the array. This wiring parasitic is a fixed-value capacitance that reduces the tuning range of the VCO.